In CMOS circuits, it is desirable to tune the threshold voltages of the n-FET devices and the p-FET devices to achieve substantially the same magnitude, which provides a balance between the n-FET and p-FET drive currents and, in turn, leads to improved device performance and circuit speed.
However, actual n-FET and p-FET threshold voltages in a CMOS circuit can be different due to various reasons. For example, if the n-FETs and the p-FETs contain metal or metal silicide gate electrodes, their threshold voltages will be significantly different, because the work function of metal or metal silicide is asymmetric with respect to the n-FETs and p-FETs. Although differentially doped polysilicon electrodes can be used in place of metal or metal silicide electrodes to reduce the threshold voltage differential between n-FETs and p-FETs, the process variations for n-FETs and p-FETs may affect the threshold voltages of the n-FETs and p-FETs differently, therefore still resulting in a certain degree of threshold voltage imbalance therebetween. Further, depending on specific transistor designs, the threshold voltages of n-FETs and p-FETs may have different temperature sensitivities. Thus, even if the threshold voltages are balanced at room temperature, imbalance may be generated subsequently during operation, because the operating temperature of the integrated circuit (IC) chip is typically 60-80 degrees higher than room temperature.
There is therefore a need for dynamic, post-fabrication adjustment of the threshold voltages of the n-FETs and p-FETs in a CMOS circuit in order to reduce the threshold voltage difference therebetween or more preferably, to achieve a substantial threshold voltage balance.